• Introduction

We are focusing on system-on-chip (SoC) technologies for mobile devices with extreme performance and energy-efficiency,
which include power-efficient neural processing unit (NPU), mobile GPU, embedded CPU, etc.
The ever increasing demand for the computing power within limited power budgets and footprints of mobile devices opens up challenges for energy-efficient SoC designs.
Therefore, lowering power and area overheads of the SoCs while increasing their performance becomes an essential technique for smart mobile devices and intelligent vehicles.
From this perspective, our goal is to increase the power and area efficiency of the SoCs as well as to improve their performance by exploring innovations
through the entire SoC design stack from algorithm, architecture, and circuit to design methodology, enabling the "intelligence on chip"

Researches in iSoC Lab include:

• Neural Processing Unit (NPU)

AI and machine learning algorithms, especially deep neural network models, demand high memory bandwidth as well as computing power
while the current von Neumann architecture of traditional processors suffers from its memory wall and serialized computation model.
Our group is exploring beyond the current von Neumann architecture for the NPUs by focusing on in-memory processing architectures and
neuromorphic computing models as well as novel memory arrays and arthmetic circuits for processing deep neural nebwork to secure
demanding memory bandwidth and energy efficiency faciltating silicon intelligence on the edge devices.

• Mobile GPU

3D computer graphics requires high computing power while mobile devices provide only imited computing resources and battery lifetime.
These contradictory constraints placed on mobile GPU design present challenges to developing power efficient mobile graphics processing devices.
To cope with this problem. we are to explore algorithmic transformation of graphics pipeline, processor architectures for graphics
stream processing, and arithmatic schemes to reduce computational complexities and thereby increasing the power-efficiency

• Embedded CPU

Recent embedded superscalar microprocessors such as ARM's Cortex-A series incorporate a lot of high-performance architectural features
such as speculative and out-of-order execution pipeline, multi-level cache system, and consistency models for the multi-core platforms.
We are to investigate several high-performance architecture and high-speed circuit design techniques including dynamic circuits, high-speed flip-flops,
and high-speed SRANs to speed up these cores to multiple GHz.

• Low-power SoC design

As the integration level of SoC is getting higher, power dissipation is becoming the major limiting factor of SoC designs for wireless mobile devices.
Therefore, sophisticated power management techniques such as power gating and body biasing to suppress static power as well as dynamic voltage
and frequency scaling to control dynamic power are widely explored.
From this perspective, we are to explore power management units and VLSI technologies together with operating system's power scheduling algorithms
exploiting a hardware and software co-optimization.